Staggered phase pulse width modulated inverter apparatus

ABSTRACT

This disclosure describes an inverter utilizing semiconductor switching devices, such as transistors or gate controlled switches, in the legs of the inverter. The legs are connected in a bridge circuit and to a source of direct current. A filter network is connected between the legs and a load across which the alternating output of the inverter is to be developed. The devices are gated on by the application of pulse width modulated signals having an actual carrier frequency to the control electrodes of the devices of the various legs of the inverter. The pulse width modulated signals are applied to the various legs in a predetermined staggered phase relationship so that the effective carrier frequency as seen by the filter network is a higher multiple of the actual carrier frequency. Thus, the filter network need only filter out the effective carrier frequency rather than the lower actual carrier frequency, while the switching devices are switched at the actual carrier frequency at high efficiency.

United States Patent [1 1 v Ravas [75] inventor: Richard J. Ravas,Monroeville, Pa. [73]- Assignee: Westinghouse Electric Corporation,

Pittsburgh, Pa.

[22] Filed: Jan. 25, 1967 21 Appl. No.: 611,697

'. '52 Us. Cl. ..321/45 R [51] Int. Cl. ..'.....H02m 7/52 [58] Field ofSearch ..32l/l6, 18,43, 45, 44, SW

' [56] v References Cited UNITED STATES PATENTS 3,378,751 4/19683,346,794 10/1967 3,409,817 11/1968 3,310,730 3/1967 3,319,147 5/19673,321,697 5/1967 3,324,376 6/1967 3,334,292 8/1967 3,376,490 4/1968OTHER PUBLICATIONS Principles of Inverter Circuits, B. D. Bedford & R.G.

Hoft, John Wiley & Sons, Inc., New York/Published Dec. 23, 1964, pp.235-247 and 310-315.

Primary Examiner-William M. Shoop, Jr.

' AttorneyF. l-l. Henson, 0. F. Renz and A. s. Oddi [57] ABSTRACT Thisdisclosure describes an inverter utilizing semiconductor switchingdevices, such as transistors or gate controlled switches, in the legs ofthe inverter. The legs are connected in a bridge circuit and to a sourceof direct current. A filter network is connected between the legs and aload across which the altemating output of the inverter is to bedeveloped. The devices are gated on by the application of pulse widthmodulated signals having an actual carrier frequency to the controlelectrodes of the devices of the various legs of the inverter. The pulsewidth modulated signals are applied to the various legs in apredetermined staggered phase relationship so that the effective carrierfrequency as seen by the filter network is a higher multiple of theactual carrier frequency. Thus, the filter network need only filter outthe effective carrier frequency rather than the lower actual carrierfrequency, while the switching devices are .switched at the actualcarrier frequency at high efficiency.

9 Claims, 7 Drawing Figures A LOAD PULSE WIDTH MODULATOR ./C|o

Wb Bn PULSE WIDTH MODULATOR to filter outall harmonics of thefundamental leaving the fundamental as a substantially pure sinusoidalwaveform at the desired output frequency. The principal disadvantage ofinverter systems of this type is that the size and weight of the filterrequired to filter out the harmonics of the output frequency becomequite large at normal output power frequencies of S to 400 Hz. In atypical embodiment of an inverter of the described type, the filter sizemay be on the order of ten times that of the output transformer rated tocarry the output power of the inverter.

1 With the advent of semiconductor devices which are capable ofswitching power at much higher frequencies than normal powerfrequencies, advantage can be taken of high frequency synthesistechniques to reduce the size and weight of inverter apparatus. One ofthe high frequency synthesis techniques is pulse width modulation,wherein a waveform having a carrier frequency of at least times that ofthe desired output frequency of the inverter is generated, and therectangular pulses of the waveform are modulated according to width sothat the resultant DC or average level of the pulse modulated waveformvaries at the desired output frequency. The pulse width modulatedwaveform is then passed through a low pass filter which has a frequencycutoff slightly below that of the carrier frequency. The resultantoutput of the inverter is a sinusoidal waveform at the desired outputfrequency. The major advantage of such a system is that the filter needonly reject the carrier frequency and its harmonies rather than theharmonics of the output frequency, which are, of course, at much lowerfrequency levels. Through such techniques it is possible to reducegreatly the physical size and weight of the filter required for use inthe inverterJIt moreover may be seen that additional advantages as tofilter size and weight can be achieved if the carrier frequency is madeas high as possible with respect .to the desired output frequency of theinverter. Power losses in semiconductor switchingdevices occur mainlyduring switching and thus it is desirable to switch the devices at aslowa frequency as possible to minimize losses. It therefore follows thatit would be highly desirable for the inverter to operate with aneffective carrier frequency higher than the actual switching frequencyof the switching devices so that the devices operate efficiently whilefilter requirements are minimized.

It is therefore an object of the present invention to provide new andimproved inverter apparatus using pulse width modulation techniques.

It is a further object to provide new and improved inverter apparatususing pulse width modulation techniques wherein the inverter apparatusis highly efficient and of minimum size and weight.

It is a still further object to provide new and improved lnverterapparatus using pulse width modulation techniques wherein the effectivecarrier frequency of the pulse width modulated waveform is increasedthrough the phase control of the switching devices of v the inverterapparatus.

Broadly, the above-cited objects are accomplished by providing inverterapparatus in which a bridge circuit is utilized including a plurality oflegs, each leg including a pair of switching devices. The switched stateof the switching device is controlled by a pulse width modulatedwaveform having a predetermined carrier frequency and an average valuewhich varies at the desired output frequency of the inverter. A filteris operative between the legs and a load, with the filter being selectedto reject all frequencies above and including a given multiple of thepredetermined carrier frequency of the pulse width modulated waveform.The pulse width modulated signals are applied to the switching devicesof the respective legs of the bridge circuit in such a phaserelationship that the effective carrier frequency appears to be themultiple of the predetermined carrier frequency that is produced by asingle leg at the bridge.

These and other objects and advantages of the present invention willbecome more apparent when considered in view of the followingspecification and drawings in which:

FIG. I is a waveform diagram of a pulse width modulated signal utilizedto explain the operation of the present invention;

FIG. 2 is a schematic diagram of one embodiment of the inverterapparatus of the present invention;

FIG. 3 is a waveform diagram including curves A, B and C which areutilized in explaining the operation of the apparatus of FIG. 2;

FIG. 4 is a schematic diagram of another embodiment of the inverterapparatus of the present invention;

FIG. 5 is a waveform diagram including curves A, B, C, D and E which areutilized to explain the apparatus shown in FIG. 4; 1 1

FIG. 6 is a frequency spectrum plot of the waveform shown in curves A,B, C or D of FIG. 5; and

FIG. 7 is a frequency spectrum plot the combined output waveform of theinverter of FIG. 4.

Referring now to FIG. 1, a pulse width modulated waveform is shown withamplitude plotted as a function of time. The pulse width modulatedwaveform has a carrier frequencyf which for example may be 10 kHz. Thecarrier frequency waveform is pulse width modulated so that the width ofthe pulses varies, as shown, so that the DC level of the compositewaveform is substantially sinusoidal as illustrated by the waveform Mwhich varies at a desired output frequency f,,, which may for example be400 Hz. By passing the pulse'width modulated waveform as shown in FIG. 1through a filter which has a frequency cutoff just below the carrierfrequency f,, an output from the filter may be obtained which will bethe waveform M and will be at the output frequency f,,. The filter willeliminate the fundamental of the carrier f as well as the harmonicsthereof. Thus, signals at the output frequency f, will be present to beapplied to a load circuit.

FIG. 2 shows a schematic diagram of an inverter utilizing pulse widthmodulated signals as well as a staggered phase technique as will now bediscussed. The inverter as shown in FIG. 2 includes a bridge circuithaving two legs a and b. The leg a includes a pair of switching devicesSla and 82a and the leg b includes a pair of switching devices Slb and82b. The switching devices Sla, S2a, Slb and 52b are illustrated to begate controlled switches (GCSs). Such a device is placed in a closedcircuit state between anode and cathode by the application of a positivepolarity pulse to the gate electrode thereof (with respect to cathode)and is placed in an open circuit condition between anode and cathode bythe application of a negative polarity pulse thereto (with respect tocathode). However, it should be understood that other semiconductorswitching devices, such as transistors, can also be utilized. The legs aand b are connected across a source of direct current which is shown inFIG. 2 as a battery E with its positive electrode connection to apositive line V+ and its negative electrode connected to a negative lineV The anode electrodes of the controlled switches Sla and Slb areconnected to the positive line V+, while the cathode electrodes of thecontrolled switches 82a and 82b are connected to the negative line V-.The cathode and anode electrodes of the devices Sla and 82a,respectively, are connected at a junction .la, and the cathode and anodeelectrodes, respectively, of the devices Slb and 82b are connected atajunction Jb.

A filter-network including an inductor Lla and a capacitor Cla isprovided, with one end of the inductor Lla connected to the junctionpoint la and the capacitor Cla connected between the other end of theinductor Lla and the V-line. An output terminal Ta for the inverter isprovided at the junction between the inductor Lla and the capacitorCla.'A filter network including an inductor Llb and capacitor Clb isprovided, with one end of the inductor Llb connected to the junction.point lb, and the capacitor Clb connected between the other end of theinductor Llb and the V- line. An output terminal Tb provides the otheroutput terminal for the inverter at the junction point between theinductor Llb and the capacitor Clb. A load circuit Z shown schematicallyby the block is connected between the output terminalsTa and Tb withalternating current of the desired output frequency f applied thereto.

The conductive state of the gate controlled switches Sla, 82a, Slb and82b is controlled by supplying a pulse width modulated signal to thegate electrodes thereof. The phase relationship between the waveformsapplied to the respective controlled switches determines which of thedevices are conductive at a given period of time. The pulse width of'theparticular pulse width modulated signal determines the time periodduring which the controlled switch passes current therethrough.

To supply the pulse width modulated signals to the control rectifiersSla and 82a of the leg a, a pulse width modulator A is provided. Theoutput of the pulse width modulator A is substantially as shown in FIG.1 and reference is also made to curve A of FIG. 3, which shows theoutput waveform of pulse width modulator A being definedas having acarrier phase of 0. The output of pulse width modulator A is supplied toa primary winding Wa of a transformer TFa. The top end of the primarywinding Wa is dotted as shown. The transformer TFa has two secondarywindings Wla and W2a. The top end of the winding Wla is dotted andcoupled through a resistor Rla to the gate electrode of the controlledswitch Sla. The undotted end of the winding Wla is connected to thecathode electrode of the switching device Sla. The bottom end of theother secondary winding W2a is dotted is connected to the cathodeelectrode of the controlled switch 82a, and the undotted end of thewinding W2 is coupled through a resistor R2a to the gate electrode ofthe switching device S2a. As can be seen from the dot convention withrespect to the windings Wa, Wla and W2a, the outputs as applied to thegate electrodes of the controlled switches Sla and 82a, respectively,are out-of-phase, and, thus, when one of the devices Sla or 82a isconductive the other device is in its non-conductive state. Hence, if ata given instant of time the pulse width modulated signal at the primarywinding Wa has a positive polarity at the dotted end thereof, a positivepolarity signal will be applied to the gate electrode, with respect tothe cathode, of the controlled switch Sla to render it conductive andpermit the translation of current from anode to cathode therethrough.Conversely, since the undotted end of the winding W2a is coupled to thegate electrode of the device S2a, this device will be maintained in anon-conductive state blocking the passage ofcurrent therethrough. Uponthe phase reversal of the pulse width modulated signal, with the dottedend of the winding Wa becoming negative, the controlled switch S2a willbe gated on, while the controlled device Sla will be turned off by theapplication of a negative polarity signal to the gate electrode thereof.

A pulse width modulator B is provided for coni trolling the gatecontrolled switches Slb and 82b of the leg b of the bridge circuit. Theoutput of the pulse width modulator B is shown in curve B of FIG. 3 andhas a phase relationship with respect to curve A of FIG. 3, the outputof the pulse width modulator A, of 180 phase difference therewith.

The output of the pulse width modulator B is applied to a primarywinding Wb of a transformer TFb. Transformer TFb has two secondarywindings Wlb and W2b. The dotted end of the winding Wlb is connected tothe cathode electrode of the gate controlled switch Slb, while theundotted end thereof is connected through a resistor Rlb to the gateelectrode of the controlled switch Slb. The dotted end of the windingW2b is coupled through a resistor R2b to the gate electrode of thecontrolled switch S2b, while the undotted end is connected to thecathode electrode thereof. The dot convention for the windings Wb, Wlband W2b is such that the pulse width modulated signals as applied fromthe winding Wb through the windings Wlb and W2b will be 180 out-of-phasewith each other. Thus, whenever the gate controlled switch Slb is gatedon by a positive polarity pulse, switch S2b will be turned off by anegative polarity pulse applied to the gate electrode thereof.

For the effective operation of the inverter apparatus, there is no needthat diagonally opposite switching devices in the legs a and b be gatedon simultaneously, that is, devices Sla and 82b or devices 82a and Slbneed not always be conductive during the same time period, in contrastto prior inverter bridge circuits. Since the filter networks Lla-Cla andLlb-Clb, to some degree, instantaneously filter out the carrierfrequency f there is no real necessity that diagonally oppositecontrolled switches be gated on and off in phase for a circuit to becompleted through the load 2 I switches of the respective legs a and bin accordance with 180 phase displaced carrier signals, the effectivecarrier frequency as seen at the junctions J1 and J2,

' may be doubled as will be shown below.

The outputs of the pulse modulators A and B, shown in curves A and B ofFIG. 3, have carrier frequency components 180 out-ofphase. The dotconventions being as established in the windings of the transformers TFaand TFb, one of the gate controlled switches in each of the legs a and bis conductive while the other switch thereof is non-conductive. Thus, asan example of this assume that at a given instant of time the output ofthe pulse width modulator A is positive at the dotted end of winding Wa,e.g. during interval t, of waveform A of FIG. 3. This will gate on thecontrolled switch Sla with the controlled switch S2b being gated off.During the same interval t the output of the pulse width modulator Bchanges from a negative value (during sube off. Immediately followinginterval t the polarity of waveform A reverses while that of waveform Bdoes not. Thus Sla will be turned off while 824: is turned on with thestates of Slb and 52b remaining the same (offand on, respectively). Theconductive period of the controlled switches Sla, Slb, 82a and 82b is,therefore, determined by the pulse width and polarity of the pulsesapplied thereto.

The waveform appearing at the junction Ja will be substantially thatshown in curve A of FIG. 3, however, at an increased power gain withrespect'to the gating pulses. V+ appears at Ja when Sla is on and 82a isoff, i.e., when waveform A is positive; and V- appears at Ja whenwaveform A is negative. The waveform appearing at the junction Jb, inthe leg b will be the inverse of that substantially as shown in curve'Bof FIG. 3, or (-B), again at an increased power gain as compared to thegate inputs thereto, because of the inversion produced by transformerTFb. V+ appears at Jb when waveform B is negative and V- appears at Jbwhen waveform B is positive.

It should be noted in curve A that the DC level is shown by the dottedcurve M which defines a sinusoidal waveform at the desired outputfrequency f,,, which for example may be 400 Hz. Curve B shows the DClevel of the pulse width modulated signal as a dotted wavefonn M whichalso takes a sinusoidal waveform at the desired outputfrequency f,,. Acomparison of the of-phase with each other.

The signal waveform as seen between junction points .Ia and Jb of therespective legs a and b of the bridge circuit is the difference betweenwaveforms appearing at filter networks as utilized in the circuit shownin FIG. 2 Y

- Ja and .lb (A(B)) A B. This difference waveform is shown in curve C ofFIG. 3. Because the waveforms A and B are out-of-phase with each other,the fundamental carrier frequency f is cancelled from the resultantwaveform as shown in curve C. The curve C shows the effective carrierfrequency of the signal to be twice that of the actual carrier frequencyf of curves A and B. Thus, the effective carrier frequency of thewaveform appearing between the junctions Ja and Jb is 2f It should benoted however that the DC level of the waveform of curve C, as shown bythe dotted waveform M", is still at the original output frequency f,,and is in phase with the modulation waveforms M and M, respectively, ofcurves A and B of FIG. 3. The end result is that the waveform C appearsto have an effective carrier frequency double that of the actual carrierfrequency. For example, if the original carrier frequency is 10 kHz theeffective carrier frequency will be 20 kHz. Waveform C would also havedouble the amplitude of A or B but for convenience of illustration, C isshown with the same maximum amplitude.

The waveforms appearing at the junction points Ja and Jb are applied tothe filter networks including the inductor Lla and the capacitor Cla andthe filter network including the inductor Llb and the capacitor Clb. Thefilter networks are selected to operate as a low pass filter to permitthe passage of the desired output frequency f therethrough to be appliedto the load Z, while eliminating other higher frequency com ponentstherefrom. However, since the effective carrier frequency 2f is doublethat of the actual carrier frequency, it is necessarily only that thecapacitors C la and C 1b be selected to by-pass therethrough frequenciesslightly below the effective carrier frequency 2f This will alsoeliminate harmonics of the effective carrier frequency 2f The inductorsLla and Llb are selected to be large enough to prevent excessiveinstantaneous device currents to flow in the switching devices Sla, 82a,Slb and 82b, but are selected also to be small enough to minimizeinductive reactance at the desired output frequency f,,.

Due to the elimination of the effective carrier frequency and itsharmonics by the filter networks Lla-Cland LlbClb, the waveform asapplied to the load Z is the DC level M, which variesin accordance withthe desired output frequency f,,. It is to be noted that the capacitancevalues of the capacitors Cla and Clb are smaller than would be requiredto eliminate the fundamental carrier frequency f,. Moreover, the

are much smaller in size and weight than would be required to filter outthe harmonics of the output frequency f, which is typically done ininverter systems. In summary of the foregoing description of theoperation of the circuit of FIG. 2, as illustrated by the waveforms ofFIG. 3, the following table is presented:

Waveform A Represents the output of pulse width modulator A and also thefonn of the voltage at point .Ia.

Represents the sine wave contained within the pulse width modulatedwaveform A and is the form of the filtered voltage appearing at pointTa.

Represents the output of pulse width modulator B. At point Jb I appearsa voltage waveform (-B) that is the inverse of B.

Represents the sine wave contained within the pulse width modulatedwaveform B. At point Tb appears a filtered voltage wavefonn (M') that isthe inverse of M'.

Represents the signal appearing across terminals Ia and lb which is thesame as A (-B) or A B.

Represents the sine wave contained within the pulse width modulatedwaveform C and is the form of the voltage appearing across terminals Taand Tb and supplied to the load Z.

In FIG. 2, diodes'Dla, D2a, Dlb and D2b are connected in reversepolarity across the gate controlled switches Sla, 82a, 8112 and 82b,respectively. That is, the cathode of a diode is connected to the anodeof a controlled switch and the anode of the diode is connected to thecathode of the controlled switch so that current may pass through thediodes in the reverse direction from the conductive direction of thegate control switches. The diodes are required to permit reactive loadsto be supplied by the inverter and provide a path current around thecontrolled switches to the DC source E. Due to the use of the inductorsLla trolled switches for proper operation of the inverter.

The techniques described with reference to the two leg bridge shown inFIG. 2 can be extended to a larger number of legs with an appropriatephase control of the switching devices within these legs. The advantageobtained by increasing the number of legs in the bridge circuit in thathigher power inverters can be provided while using low power switchingdevices. Additional advantages will be pointed out in the discussion ofFIG. 4 which-follows immediately.

FIG. 4'is a schematic diagram of a four leg inverter system includinglegs a, b, c, and d and wherein each of the legs are controlled byapplying pulse width modulated signals thereto in a predetermined phaserelationship to one another. Each of the legs a, b, c and d of thebridge circuit shown in FIG. 4 are substantially identical and areconnected across a source of direct current indicated as a battery Ewhich has its positive electrodes connected at the V+ line and itsnegative electrode connected at the V line. Each of the legs include apair of transistors: transistors Q10 and Q2a are connected in leg a;transistors Qlb and 02b in leg b; transistors Q10 and Q20 in leg c; andtransistors Old and 02d in leg d. The transistors are shown to be of theNPN type, however, a PNP type could be utilized with the appropriatechange in polarity in the driving potential therefor. The transistorsare operative in a switching mode to translate current from the directcurrent source E to a load Z.

A pulse width modulator is provided to control the conductive states ofthe transistors in each of the legs of of the pulse width modulator A as0, the output of the pulse width modulator B is delayed 180 therefrom;the pulse width modulator C is delayed therefrom; and the pulse-widthmodulator D is delayed 270 therefrom. The pulse width modulated signalsupplied by the modulators A, B, C and D are at a predetermined carrierfrequency f which for example may be 10 kHz.

Since the circuitry associated with each of the legs of the inverter issubstantially identical only the specific circuitry of leg a will bediscussed for illustrative purposes. Also, similar reference characterswith respect to FIG. 2 are used for the corresponding components in FIG.4. The pulse width modulator A supplies a pulse width modulated outputto the primary winding Wa of the transformer TFa, with the waveformbeing substantially as shown in curve A of FIG. 3 having a carrierfrequency of f, and a DC level such as shown in the waveform M varyingat the desired output frequency f,,. The transformer TFa includes twosecondary windings Wla and W2a. The dotted end of the winding Wla isconnected to the anode of a diode D3a with the cathode of the diodeconnected to the collector of the transistor Qla. The collector of thetransistor Qla is connected to the V+ line, while the emitter electrodethereof is coupled through a resistor R3a to the bottom end of thewinding Wla. The base electrode of the transistor Qla is connected to atap on the winding Wla. A diode D4a is connected directly across theresistor R30 with its cathode connected to the emitter electrode of thetransistor Qla. The tapped connection of the transistor Qla to thesecondary winding Wla permits the non-saturated operation of thetransistor Qla. Assume that the transistor Qla is initially blocking.There is a current flow into the base elec- .trode of the transistor Qlawhich is limited by the voltage developed across the transformer windingWla between the tap and the bottom end thereof divided by the resistanceof the resistor R311. If the load current of the transistor Qla is at asmall enough level so that the transistor Qla will go into saturation,current will tend toflow through the diode D3a to the collectorelectrode of the transistor Qla. This diverts current from thebase ofthe transistor to the collector thereof thus reducing the base driveuntil the collector voltage increases several volts and permits basedrive for the transistor again. Stable non-saturated operation is thusobtained with base drive just sufficient to maintain a slight voltagedrop from collector to emitter of the transistor Qla. The operation ofthe transistor Q10 in a non-saturating mode permits maximum switchingspeed to be obtained. Increased switching speed is also obtained byplacing the diode D4a across the resistor R3a to permit maximum turn offdrive to be applied to the transistor Qla at the end of a conduction ininterval.

The other transistor Q2a in the leg a has its base electrode connectedto a tap on the secondary winding W2a. The emitter electrode thereof isconnected to the V- line and the collector is connected to the cathodeof a diode D5a, which has its anode connected at the undotted end of thewinding W2a. The dotted end of the winding W2a is connected through theresistor R4a to the emitter electrode of the transistor Q2a. A diode D6ais connected across the resistor R4a with the cathode electrode thereofconnected to the emitter of the transistor Q2a. The operation of thetransistor 02a is identical to that of the transistor Qla, however withthe dot convention as established with reference to the primary windingWa of the transformer TFa being such that whenever the transistor Qla isin its conductive state the transistor Q2a is in its blocking state andvice versa.

When transistors are connected as shown in FIG. 4, one transistor mayturn on before the other has fully regained full blocking capability. Inorder to prevent a short circuit, even for this very short interval oftime, an inductor L2a is connected between the emitter of the transistor01a and the junction Ja, and an inductor L30 is connected between thecollector of the transistor 02a and the junction Ja.

The voltage appearing at the junction .la is essentially the pulse widthmodulated waveform which is to be synthesized to form the outputalternating current applied to the load Z. The output appearing at thejunction Ja is, of course, greatly increased in power in comparison tothe pulse width modulated signals used to gate the transistors of theinverter circuit. A filter network including the inductor Lla andcapacitor Cla is connected to the junction Ja. The inductor Lla isselected-to prevent excessive instantaneous transistor current to flowthrough the transistor Qla and Q2a. The inductor L12 is also selected tobe small enough to minimize reactance at the output frequency f,,.

The capacitor Cla is connected between the inductor Lla and the V- lineand is selected to provide a bypass to high frequency signals. Theinductor Lla and capacitor Cla act as the filter network as discussedwith reference to FIG. 2. The output of the filter network Lla-Cla isconnected through a capacitor C2a to an output terminal Tab of theinverter which is connected to the load Z. The capacitor C20 is of theelectrolytic type to provide DC blocking which is necessary in theinverter circuit since no provision is made therein to regulatecritically the DC voltage level at the outputs of the four legs a, b, cand d. The value for the capacitor C2a is selected to be somewhatsmaller than to have negligible capacitive reactance at the desiredoutput frequency f,, and thereby tends to cancel out the inductivereactance of the filter inductor Lla. By so selecting the capacitor C2a,a low impedance output stage is achieved. A diode D7a is connectedacross the capacitor C2a with its cathode toward the inductor Lla. Aresistor R5a is also connected across the capacitor C2a, while aresistor R6ab is connected from the capacitor CZaand terminal Tab to theV line. The function of the diode D7a and the resistors R5a and R60!) isto insure that the electrolytic capacitor C2a is properly biased.

In order that the system is capable of carrying reactive power, diodesDla, D2a, D80 and D9a are utilized. The diode DIa is connected fromanode to cathode between the emitter and collector electrodes,respectively, of the transistor Qla. The diode D8a is connected fromanode to cathode between the V line and the emitter of the transistorQla. The diode D2a is connected from anode to cathode between theemitter and collector electrodes of the transistor 02a, and the diodeD9a is connected from anode to cathode between the collector electrodes,respectively, of the transistors 02a and Ola. These diodes permit areverse current path to the battery E around the reverse directions ofthe transistors Qla and Q2a. Because the change of voltage with timeacross the diodes D8a and D9a is quite large, it is preferable thatthese diodes be of a fast recovery type.

The circuitry of the other three legs b, c and d of th inverter shown inFIG. 4 is similarly arranged and function identically to that of leg a.At the output junction Jb of the leg b, pulse width modulated signalsare developed which are similar in waveform to that shown in FIG. 1 andwhich are 180 out-of-phase with the waveform appearing at the junction1a of the leg a. The output of the leg b from the junction M is suppliedthrough the filter network including the inductor Llb and capacitor Clbthrough the coupling capacitor C2b to the output terminal Tab. At theoutput junction Jc of the leg c, a waveform similar to that shown inFIG. 1 is developed having a phase relationship of from that of the lega appearing at the junction Ja. This'output is supplied through thefilter network including Llc and the capacitor Clc, and is then appliedthrough the coupling capacitor C2c to the other output terminal of theinverter Ted. The output of the leg 11 appears at the junction and has awaveform such as shown in FIG. I, however, displaced 270 from the outputof the junction Ia of the leg a. This output is applied through thefilter network including the inductor Lld and the capacitor Cld and thenthrough the coupling capacitor C2d to the output terminal Ted. Thecombined outputs of the four legs a, b, c and d are thus applied acrossthe load Z with the outputs at junctions Ja and Jb being added and. theoutputs from the junctions Ia and Jd being substracted therefrom.

FIG. 5 in curves A, B, C and D shows a waveform diagram of the outputsappearing respectively at the junctions Ja, Jb, Jo and Jd of the legs a,b, c and d. The frequency of the waveforms in curves A, B, C and D isthat of the carrier frequency f,. However, by taking the algebraic sumof the waveforms of curves A, B, C and D a composite waveform such asshown in curve B of FIG. 5 is obtained. It can be seen that the waveformE is at four times the carrier frequency f,, with the first, second andthird harmonics of the carrier frequency being cancelled in thesummation of these waveforms.

This is better seen by reference to FIGS. 6 and 7. FIG. 6 shows afrequency spectrum plot of a waveform such as shown in curves A, B, C orD of FIG. 5. The fundamental carrier frequency f is shown to be 9.6kHz., the first, second, third and fourth harmonics being, respectively;19.2 kHz., 28.8 kHz. and 38.4 kHz. The presence of relatively highamplitude components appearing at these frequencies is shown on the plotof FIG. 6. Relatively high amplitude components are also shown to appearat fifth and sixth harmonic frequency of the 9.6 kHz. fundamental. The400 Hz power output frequency f is also shown.

FIG. 7 is a frequency spectrum plot of the combined output voltageappearing at the junctions Ja, Jb; Jc and Id of the inverter of FIG. 4using the staggered phase cancelling technique as described herein. Ascan be seen fromthe plot, the power output frequency of 400 Hz appears;however, the first, second and third harmonies have been cancelled. Thefourth harmonic is the first to appear in plot. The fifth and sixthharmonics also do not appear in the plot.

The fourth harmonic of the fundamental frequency thus appears as theeffective carrier frequency of the inverter. The filter network mustthen only eliminates frequencies above approximately four times, thefundamental, or in the present example, have a low frequency cutoff ofslightly lower than 38.4 kHz., with a fundamental frequency of 9.6 kHz.It should also be noted that the frequency about 38.4 kHz. in FIG. 7 isof a relatively low amplitude as compared to the fundamental and othercomponents of the spectrum as shown in FIG. 6. Hence, the filter with aspectrum as shown in FIG. 7 is only required to attenuate a relativelylow amplitude signal. Thus, the effective carrier frequency of thewaveform shown in curve E of FIG. is four times the actual carrierfrequency of 4f .It is only necessary to eliminate the effective carrierfrequency 4f from the waveform E in order to synthesize the desiredoutput frequency f,,. The capacitors Cla, Clb, C10 and Cld thus can berelatively small and need only shunt frequencies above and includingfour times the actual carrier frequency f Therefore, through the use ofthe four leg inverter circuit and the'appropriate application of pulsewidth modulated signals to control the gating of the' transistors usedin each of the legs, an inverter circuit having an effective carrierfrequency of four times the actual carrier frequency can be providedwith the at-.

tendant advantage of reducing the size of the filter network needed tosynthesize the sinusoidal output signal at the desiredoutput frequencyf,,. Of course, more legs could be added to the bridge, with theincreased power capacity and reduced filter size being obtained with theappropriate phase relationship being maintained between the various legsof the inverter. The effective carrier frequency will be equal to thenumber of legs times the actual carrier frequency.

Although the present invention has been described with a certain degreeof particularity, it should be understood that the present disclosurehasbeen made only by way of example and that numerous changes in thecombination and arrangement of parts and elements can be resorted towithout departing'from the scope and spirit of the present invention.

I claim: I

1. In inverter apparatus operative with a source of direct current forsupplying a load circuit with alternating current having a predeterminedoutput frequency, the combination of:

a bridge circuit including a plurality of legs connected operativelyacross said source ofdirect current,

each of said legs including a pair of switching devices operativelyconnected and operative to be placed in a selected open or closedcircuit switched state;

means for providing pulse width modulated signals having a predeterminedcarrier frequency and being so modulated to have an average valuevarying at said predetermined output frequency;

means for applying said pulse width modulated signals to said switchingdevices of said plurality of legs, respectively, in a predeterminedphase relationship so that said devices in each of said legs are placedin an open or closed circuit switch state in response thereto; and

filter means operatively connecting said legs of said bridge circuit andsaid load circuit,

said filter means being so selected to reject frequencies above andincluding a given multiple of said predetermined carrier frequency, saidpredetermined phase relationship being such that said predeterminedcarrier frequency does not appear across said load circuit and theeffective carrier frequency appears to be said multiple of saidpredetermined frequency that is rejected by said filter means with saidalternating current having a predetermined output frequency beingapplied to said load circuit.

2. In the inverter apparatus of claim 1 wherein:

whenever one of said pair of said switching devices is placed in aclosed circuit switched state the other of said pair is placed in anopen circuit switched state,

predetermined ones of said pair of said switching devices in each ofsaid legs being placed in the same switched state during the same periodof time.

3. In the inverter apparatus of claim 2 wherein:

said bridge circuit including a first and a second leg connected on theopposite sides of said bridge circuit,

each of said legs including a first and a second switching deviceconnected in series with a junction formed therebetween,

said filter means operatively connected between said junctions in eachof said legs and said load,

said predetermined phase relationship for said pulse width modulatedsignals applied to said switching devices in said first and second legsbeing substantially 180 out of phase with each other,

said first and said second devices of said first and second legsrespectively being placed in the same switched state during the sameperiod of time,

said given multiple of said predetermined carrier frequency being two.

4. In the inverter apparatus of claim 2, wherein:

said bridge circuit including first, second, third and fourth legs, saidfirst and said second legs being connected on one side of bridge circuitand said third and fourth legs being connected on the other sidethereof,

said predetermined phase relationship for said pulse width modulatesignals being applied to said switching devices of said first, second,third and fourth legs, respectively being substantially 0, 180, and 270,

said given multiple of said predetermined carrier frequency being four.

5. In the inverter apparatus of claim 2 wherein:

said switching devices comprise gate controlled switches.

6. In theinverter apparatus of claim 2 wherein:

said switching devices comprise transistors operative in a switchingmode.

7. In the inverter apparatus of claim 6, further including:

means for preventing said transistors from going into saturation so asto decrease the switching time thereof.

8. In the inverter apparatus of claim 2, further including:

a unidirectional device connected across each of said switching devicesto provide a reverse current path

1. In inverter apparatus operative with a source of direct current forsupplying a load circuit with alternating current having a predeterminedoutput frequency, the combination of: a bridge circuit including aplurality of legs connected operatively across said source of directcurrent, each of said legs including a pair of switching devicesoperatively connected and operative to be placed in a selected open orclosed circuit switched state; means for providing pulse width modulatedsignals having a predetermined carrier frequency and being so modulatedto have an average value varying at said predetermined output frequency;means for applying said pulse width modulated signals to said switchingdevices of said plurality of legs, respectively, in a predeterminedphase relationship so that said devices in each of said legs are placedin an open or closed circuit switch state in response thereto; andfilter means operatively connecting said legs of said bridge circuit andsaid load circuit, said filter means being so selected to rejectfrequencies above and including a given multiple of said predeterminedcarrier frequency, said predetermined phase relationship being such thatsaid predetermined carrier frequency does not appear across said loadcircuit and the effective carrier frequency appears to be said multipleof said predetermined frequency that is rejected by said filter meanswith said alternating current having a predetermined output frequencybeing applied to said load circuit.
 1. In inverter apparatus operativewith a source of direct current for supplying a load circuit withalternating current having a predetermined output frequency, thecombination of: a bridge circuit including a plurality of legs connectedoperatively across said source of direct current, each of said legsincluding a pair of switching devices operatively connected andoperative to be placed in a selected open or closed circuit switchedstate; means for providing pulse width modulated signals having apredetermined carrier frequency and being so modulated to have anaverage value varying at said predetermined output frequency; means forapplying said pulse width modulated signals to said switching devices ofsaid plurality of legs, respectively, in a predetermined phaserelationship so that said devices in each of said legs are placed in anopen or closed circuit switch state in response thereto; and filtermeans operatively connecting said legs of said bridge circuit and saidload circuit, said filter means being so selected to reject frequenciesabove and including a given multiple of said predetermined carrierfrequency, said predetermined phase relationship being such that saidpredetermined carrier frequency does not appear across said load circuitand the effective carrier frequency appears to be said multiple of saidpredetermined frequency that is rejected by said filter means with saidalternating current having a predetermined output frequency beingapplied to said load circuit.
 2. In the inverter apparatus of claim 1wherein: whenever one of said pair of said switching devices is placedin a closed circuit switched state the other of said pair is placed inan open circuit switched state, predetermined ones of said pair of saidswitching devices in each of said legs being placed in the same switchedstate during the same period of time.
 3. In the inverter apparatus ofclaim 2 wherein: said bridge circuit including a First and a second legconnected on the opposite sides of said bridge circuit, each of saidlegs including a first and a second switching device connected in serieswith a junction formed therebetween, said filter means operativelyconnected between said junctions in each of said legs and said load,said predetermined phase relationship for said pulse width modulatedsignals applied to said switching devices in said first and second legsbeing substantially 180* out of phase with each other, said first andsaid second devices of said first and second legs respectively beingplaced in the same switched state during the same period of time, saidgiven multiple of said predetermined carrier frequency being two.
 4. Inthe inverter apparatus of claim 2, wherein: said bridge circuitincluding first, second, third and fourth legs, said first and saidsecond legs being connected on one side of bridge circuit and said thirdand fourth legs being connected on the other side thereof, saidpredetermined phase relationship for said pulse width modulate signalsbeing applied to said switching devices of said first, second, third andfourth legs, respectively being substantially 0*, 180*, 90* and 270*,said given multiple of said predetermined carrier frequency being four.5. In the inverter apparatus of claim 2 wherein: said switching devicescomprise gate controlled switches.
 6. In the inverter apparatus of claim2 wherein: said switching devices comprise transistors operative in aswitching mode.
 7. In the inverter apparatus of claim 6, furtherincluding: means for preventing said transistors from going intosaturation so as to decrease the switching time thereof.
 8. In theinverter apparatus of claim 2, further including: a unidirectionaldevice connected across each of said switching devices to provide areverse current path thereacross so that said inverter may be operativewith reactive loads.